Minimizing total weighted tardiness on a single batch process machine with incompatible job families

The di0usion step in semiconductor wafer fabrication is very time consuming, compared to other steps in the process, and performance in this area has a signi1cant impact on overall factory performance. Di0usion furnaces are able to process multiple lots of similar wafers at a time, and are therefore appropriately modeled as batch processing machines with incompatible job families. Due to the importance of on-time delivery in semiconductor manufacturing, we focus on minimizing the total weighted tardiness in this environment. The resulting problem is NP-Hard, and we decompose it into two sequential decision problems: assigning lots to batches followed by sequencing the batches. We develop several heuristics for these subproblems and test their performance. ? 2003 Elsevier Ltd. All rights reserved.